News Intel details new advanced packaging breakthroughs — EMIB-T paves the way for HBM4 and increased UCIe bandwidth

[Admin]

Intel disclosed several chip packaging breakthroughs at the Electronic Components Technology Conference (ECTC), outlining the technical merits of multiple new chip packaging techniques that the company plans to deploy in production in the future.

Intel details new advanced packaging breakthroughs — EMIB-T paves the way for HBM4 and increased UCIe bandwidth : Read more

 

[thestryker]

It's really interesting to see the innovations being made for the huge sizes enterprise level chips have gotten to. Hopefully some of the connectivity advances will make its way down to

For whatever reason when I'd read about EMIB-T before my brain just didn't put two and two together that the TSVs were through the EMIB silicon itself. I thought it was supposed to make its debut with CWF, but that doesn't seem to be the case. It'll be interesting to see if maybe there will be a DMR "Max" like we saw with SPR.

 

[Pierce2623]

I hope they end up with actual volume capabilities in the 2.5d stuff. I feel like Arrow Lake/Lunar Lake already approached the maximum bandwidth available on their currently used interposer technology. Core to core latency through the interposer was terrible for cores on a seperate die on Lunar Lake and LL is generally much better on latency than Arrow Lake.

 

[thestryker]

I hope they end up with actual volume capabilities in the 2.5d stuff. I feel like Arrow Lake/Lunar Lake already approached the maximum bandwidth available on their currently used interposer technology. Core to core latency through the interposer was terrible for cores on a seperate die on Lunar Lake and LL is generally much better on latency than Arrow Lake.

LNL/ARL didn't use EMIB and the chances of anything client using it are pretty low. Everything was placed on a base tile utilizing Foveros, and there are several different versions of that. It's more likely latency is a design level issue rather than interconnect because Intel's physical interconnect is superior to AMD's.

 

[acadia11]

So the more I think about it, Intel should really spin off foundry unit as a subsidiary or separate company. No partner is really going to trust Intel if they are also competing with Intel for resources as a contract client. Samsung and TSMC are its main competitors on the foundry side but you notice TSMC doesn’t compete with its clients but serves them. And this is one of the reasons they are massively successful. Samsung does but it has proven track record as a sourcing partner.

 

[TerryLaze]

So the more I think about it, Intel should really spin off foundry unit as a subsidiary or separate company. No partner is really going to trust Intel if they are also competing with Intel for resources as a contract client. Samsung and TSMC are its main competitors on the foundry side but you notice TSMC doesn’t compete with its clients but serves them. And this is one of the reasons they are massively successful. Samsung does but it has proven track record as a sourcing partner.

What exactly is the trust that partners are going to have???
Everybody is going to keep using tsmc and then intel additionally to that so they won't have to worry about losing out on selling stuff.
And if intel doesn't provide them the amount of product they agreed upon they will be able to sue intel because everything is done with contracts.

Intel isn't some shady 3rd country business nobody has heard about before, they have 50+ years of business relations to everybody in the business.

 

[thestryker]

So the more I think about it, Intel should really spin off foundry unit as a subsidiary or separate company. No partner is really going to trust Intel if they are also competing with Intel for resources as a contract client. Samsung and TSMC are its main competitors on the foundry side but you notice TSMC doesn’t compete with its clients but serves them. And this is one of the reasons they are massively successful. Samsung does but it has proven track record as a sourcing partner.

This isn't a viable business plan until the vast majority of Intel's silicon production uses industry standard tools. Perhaps 2027-2028 at the very earliest, but I wouldn't be surprised if the future was already locked in by then.

 

[acadia11]

This isn't a viable business plan until the vast majority of Intel's silicon production uses industry standard tools. Perhaps 2027-2028 at the very earliest, but I wouldn't be surprised if the future was already locked in by then.

18A is “supposedly” following industry standard specifications , but yes 14A is supposedly when Intel feels it will have made the full transition as a partner foundry.

 

[thestryker]

18A is “supposedly” following industry standard specifications , but yes 14A is supposedly when Intel feels it will have made the full transition as a partner foundry.

EUV isn't the problem, as all of their EUV nodes are standardized, it's the DUV nodes that are the problem. They have a massive amount of DUV capacity and outside of Intel 16 (a modified 22nm) none of them adhere to standards. There's also a forthcoming 'Intel 12' node they're developing with UMC which has been forecast for ~2027. They have to be able to covert a majority of their DUV capacity before the foundry business could be viable on its own.

 

[Pierce2623]

LNL/ARL didn't use EMIB and the chances of anything client using it are pretty low. Everything was placed on a base tile utilizing Foveros, and there are several different versions of that. It's more likely latency is a design level issue rather than interconnect because Intel's physical interconnect is superior to AMD's.

I’m aware they didn’t use EMIB. That’s my point. Their current client interposer solution sucks.

 

[Pierce2623]

EUV isn't the problem, as all of their EUV nodes are standardized, it's the DUV nodes that are the problem. They have a massive amount of DUV capacity and outside of Intel 16 (a modified 22nm) none of them adhere to standards. There's also a forthcoming 'Intel 12' node they're developing with UMC which has been forecast for ~2027. They have to be able to covert a majority of their DUV capacity before the foundry business could be viable on its own.

That 12nm could be their golden goose for cheap commercial chip production too.

 

[acadia11]

EUV isn't the problem, as all of their EUV nodes are standardized, it's the DUV nodes that are the problem. They have a massive amount of DUV capacity and outside of Intel 16 (a modified 22nm) none of them adhere to standards. There's also a forthcoming 'Intel 12' node they're developing with UMC which has been forecast for ~2027. They have to be able to covert a majority of their DUV capacity before the foundry business could be viable on its own.

Yes, Intel trailing edge tech it’s known that it’s not standardized and basically it’s throwaway unless Intel is building for itself. This has been part of their problem with their foundry even their trailing edge tech doesn’t live but for 1 or 2 generations, … I do not believe they will invest in their trailing edge and more importantly they aren’t going to do that better than chinas fabs and others in this domain. I understand the UMC deal will be a new trailing edge process but it won’t be using existing as you pointed out. It’s a gamble there are many competitors in that space and all of them are better FAB partners than Intel. It gives Intel a complete stack but IMHO leading edge is where it’s at, there are only a few companies in the world with the tech … and that’s where all the money and margin is at the moment … sure IOT, and General Electronics will grow but TSMC is TSMC because they own the leading edge market … but do support full stack leading and trailing edge capabilities.